Conventionally, there has been known a MOSFET which includes a semiconductor base body where a trench having a predetermined depth is formed on a surface of an n-type semiconductor layer, and a p-type semiconductor layer formed of an epitaxial layer is formed in the inside of the trench (see patent literature 1, for example).
As shown in FIG. 21, the conventional MOSFET 700 is a planar gate type MOSFET including: a semiconductor base body 710 where an n−-type second semiconductor layer 714 is stacked on an n+-type first semiconductor layer 712, a plurality of trenches 718 having a predetermined depth which are arranged along a predetermined direction are formed on a surface of the second semiconductor layer 714, a p−-type third semiconductor layer 716 formed of an epitaxial layer is formed in the inside of the trench 718 (see semiconductor base body 710′ shown in FIG. 22), a p-type base layer 720 is formed on a portion of a surface of the second semiconductor layer 714 and a whole surface of the third semiconductor layer 716, and an n-type first-conductive-type high concentration diffusion region 740 (source region 740) is formed on a portion of a surface of the base layer 720; a first electrode 726 (drain electrode) which is positioned on a surface of the first semiconductor layer 712; an interlayer insulation film 722 which is positioned on a surface of the second semiconductor layer 714 and on a surface of the third semiconductor layer 716 and has a predetermined opening 728 formed within a region where the third semiconductor layer 716 is formed as viewed in a plan view; a second electrode 724 (source electrode) which is positioned over the interlayer insulation film 722; and a gate electrode 744 which is formed so as to cover at least a base layer 720 sandwiched between the source region 740 and the second semiconductor layer 714 by way of a gate insulation film 742.
In the conventional MOSFET 700, assuming a portion of a region of the second semiconductor layer 714 sandwiched between the trenches 718 disposed adjacently to each other and deeper than the base layer 720 as a first column 1C, and a portion of the third semiconductor layer 716 deeper than the base layer 720 as a second column 2C, and a super junction structure is formed of the first column 1C and the second column 2C.
In the conventional MOSFET 700, metal for forming the second electrode 724 is filled into the inside of the opening 728 directly, and the second electrode 724 is directly connected to the third semiconductor layer 716 (to be more specific, the source region 740 and the base layer 720).
In such a conventional MOSFET 700, the third semiconductor layer 716 is formed by forming the trench 718 in the second semiconductor layer 714 and by filling the trench 718 with a p-type epitaxial layer.
According to the conventional MOSFET 700, since the super junction structure is formed of the first column 1C and the second column 2C as viewed in a plan view and hence, it is possible to provide a MOSFET having a high breakdown strength and a low ON voltage.